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Friday, December 8, 2023

Accelerating RISC-V growth with network-on-chip IP

On this planet of system-on-chip (SoC) units, architects encounter many choices when configuring the processor subsystem. Decisions vary from single processor cores to clusters to a number of core clusters which might be predominantly heterogeneous however often homogeneous.

A current development is the widespread adoption of RISC-V cores, that are constructed upon open customary RISC-V instruction set structure (ISA). This method is obtainable by royalty-free open-source licenses.

Right here, the utilization of network-on-chip (NoC) applied sciences’ plug-and-play capabilities has emerged as an efficient technique to speed up the mixing of RISC-V-based programs. This method facilitates seamless connections between processor cores or clusters and mental property (IP) blocks from a number of distributors.


Community-on-chip fundamentals

Utilizing a NoC interconnect IP presents a number of benefits. The NoC can prolong throughout the entire machine, with every IP having a number of interfaces that span the whole SoC. These interfaces have their very own knowledge widths, function at various clock frequencies, and make the most of numerous protocols similar to OCP, APB, AHB, AXI, STBus, and DTL generally adopted by SoC designers. Every of those interfaces hyperlinks to a corresponding community interface unit (NIU), additionally known as a socket.

The NIU’s function is to obtain knowledge from a transmitting IP after which arrange and serialize this knowledge right into a standardized format appropriate for community transmission. A number of packets may be in transit concurrently. Upon arrival at its vacation spot, the related socket performs the reverse motion by deserializing and undoing the packetization earlier than presenting the info to the related IP. This course of is completed in accordance with the protocol and interface specs linked to that exact IP.

A simple illustration of IP blocks might be visualized as stable logic blocks. Moreover, an SoC often makes use of a single NoC. Determine 1 illustrates a fundamental NoC configuration.

Determine 1 A quite simple NoC illustration reveals fundamental design configuration. Supply: Arteris

The NoC itself may be carried out utilizing a wide range of topologies, together with 1D star, 1D ring, 1D tree, 2D mesh, 2D torus and full mesh, as illustrated in Determine 2.

Determine 2 The above examples present a wide range of NoC topologies. Supply: Arteris

Some SoC design groups might need to develop their very own proprietary NoCs, a course of that’s resource- and time-intensive. This method requires groups of a number of specialised engineers to work for 2 or extra years. To make issues tougher, designers usually make investments almost as a lot time debugging and verifying an in-house developed NoC as they do for the remainder of the whole design.

As design cycles shorten and time-to-revenue pressures enhance, SoC growth groups are contemplating commercially obtainable NoC IP. This IP permits the customization required in an internally developed NoC IP however is obtainable from third-party distributors.

One other problem of the rising SoC complexity is the follow of using a number of NoCs and varied NoC topologies inside a single machine (Determine 3). As an example, one part of the chip may undertake a hierarchical tree topology, whereas one other space may go for a 2D mesh configuration.

Determine 3 The illustration highlights sub-system blocks with inside NoCs. Supply: Arteris

In lots of instances, the IP blocks in at this time’s SoCs are the equal of complete SoCs of just a few years in the past, making them sub-systems. Thus, the creators of those sub-system blocks will usually select to make use of industry-standard NoC IP supplied by a third-party vendor.

In situations requiring excessive ranges of customizability and co-optimization of compute and knowledge transport, similar to a processor cluster or a neural community accelerator, the IP growth group might go for a customized implementation of the transport mechanisms. Alternatively, they could determine to make the most of one of many lesser adopted, extremely specialised protocols to realize their design objectives.

RISC-V and NoC integration

For a standalone RISC-V processor core, these IPs can be found with AXI interfaces for designers who don’t want coherency and CHI interfaces for many who do. This enables these cores to plug-and-play with an industry-standard NoC on the SoC degree.

Likewise, if design groups choose one of many much less generally adopted protocols for inter-cluster communication in a RISC-V design, that cluster also can characteristic ACE, AXI or CHI interfaces towards exterior connections. This methodology permits for fast connection to the SoC’s NoC.

Determine 4 beneath options each non-coherent and cache coherent choices. In addition to their utilization in IPs and SoCs, these NoCs also can perform as tremendous NoCs inside multi-die programs.

Determine 4 A NoC interconnect IP is proven within the context of a multi-die system. Supply: Arteris

NoC IP in RISC-V processors

The {industry} is experiencing a dramatic upsurge in SoC designs that includes processor cores and clusters primarily based on the open customary RISC-V instruction set structure.

The event and adoption of RISC-V-based programs, together with multi-die programs, may be accelerated by leveraging the plug-and-play capabilities supplied by NoC applied sciences. This allows fast, seamless and environment friendly connections between RISC-V processor cores or clusters and IP practical blocks supplied by a number of distributors.

Frank Schirrmeister, VP options and enterprise growth at Arteris, leads actions within the automotive, knowledge middle, 5G/6G communications, cellular, aerospace and knowledge middle {industry} verticals. Earlier than Arteris, Frank held varied senior management positions at Cadence Design Programs, Synopsys and Imperas, specializing in product advertising and administration, options, strategic ecosystem accomplice initiatives and buyer engagement.

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