Location: Noida
Firm: Qualcomm
Normal Abstract
As a number one expertise innovator, Qualcomm pushes the boundaries of what’s potential to allow next-generation experiences and drives digital transformation to assist create a better, related future for all. As a Qualcomm {Hardware} Engineer, you’ll plan, design, optimize, confirm, and take a look at digital programs, bring-up yield, circuits, mechanical programs, Digital/Analog/RF/optical programs, tools and packaging, take a look at programs, FPGA, and/or DSP programs that launch cutting-edge, world class merchandise. Qualcomm {Hardware} Engineers collaborate with cross-functional groups to develop options and meet efficiency necessities.
Minimal {Qualifications}
Bachelor’s diploma in Laptop Science, Electrical/Electronics Engineering, Engineering, or associated area and 4+ years of {Hardware} Engineering or associated work expertise.
OR
Grasp’s diploma in Laptop Science, Electrical/Electronics Engineering, Engineering, or associated area and three+ years of {Hardware} Engineering or associated work expertise.
OR
PhD in Laptop Science, Electrical/Electronics Engineering, Engineering, or associated area and a pair of+ years of {Hardware} Engineering or associated work expertise.
Required to work on IP / Subsystem stage verification and personal varied DV duties from Take a look at plan creation, protection mannequin improvement, take a look at case writing and protection closure.
Expertise: UVM, SV, SVA (assertions)
Anticipated to do full triage’ing in collaboration with design staff and proactively report standing of progress
Must be proficient in System-Verilog and scripting language like Shell, Perl . Should have RTL/gate stage simulation debug expertise. Ought to have a working data of bus protocols like AHB/AXI . candidates ought to have 5-8 years expertise.
very sharp in debugging
good in SV, UVM, Assertions, GLS
Capable of be part of ASAP (in lower than 2 weeks)
Must be proficient in System-Verilog and scripting language like Shell, Perl . Should have RTL/gate stage simulation debug expertise. Ought to have a working data of bus protocols like AHB/AXI . candidates ought to have 5-8 years expertise
- Fingers on data/expeience in System verilog and UVM
- Stable data of C and Scipting language like python
- Should have RTL and Gate stage simulation debug expertise
- Working data of bus protocol like AHB/AXI
