One of many main targets for the facility provide trade is to convey greater energy conversion effectivity and energy density to energy units in functions comparable to knowledge facilities and 5G. Integrating a driver circuit and energy MOSFET—often called a DrMOS—into an IC will increase energy density and effectivity when in comparison with a traditional, discrete MOSFET with a person driver IC.
Furthermore, DrMOS’s flip-chip expertise additional optimizes the voltage regulator’s efficiency by lowering response time and lowering the inductance between the die and package deal (Determine 1).
Determine 1 Here’s a comparability between typical wire bond and flip-chip expertise. Supply: Monolithic Energy Techniques
Nevertheless, parasitic inductance on the substrate and PCB considerably impacts the drain-to-source voltage (VDS) spike, and that’s attributable to resonance between parasitic inductance and MOSFET’s output capacitance (COSS). A excessive VDS spike may cause a MOSFET avalanche, which results in system degradation and reliability points. To forestall an avalanche breakdown on the MOSFET, there are a number of strategies to alleviate voltage stress.
The primary methodology is to use a higher-voltage, double-diffused MOSFET (DMOS) course of on the DrMOS. If this course of is adopted within the energy MOSFET design, it leads to a better on resistance (RDS(ON)) for the DrMOS attributable to a decreased variety of paralleled DMOS inside the identical area.
The second methodology is to make use of a snubber circuit to suppress voltage spike. Nevertheless, this methodology results in additional loss on snubber circuit. Moreover, including a snubber circuit could not successfully decrease the MOSFET’s VDS spike because the stray inductance that causes resonant conduct is especially built-in in DrMOS’s package deal.
When making an attempt to extend voltage regulator effectivity and cut back the MOSFET’s voltage spikes, the tradeoffs described above could make it troublesome to quantify and optimize the consequences of parasitic inductance on the PCB and substrate.
This text will first focus on parasitic inductance modeling. Subsequent, the equal parasitic circuit mannequin is utilized in a SPICE simulation device to foretell the VDS switching spike. Experimental outcomes might be introduced to confirm the feasibility of the parasitic mannequin.
Parasitic inductance modeling on a DrMOS
To mannequin parasitic inductance, 3D constructions of each the DrMOS and PCB have been constructed for a simulation evaluation (Determine 2). Parameters comparable to the fabric, stack-up data and PCB in addition to package deal layer thickness are essential for modeling accuracy.
Determine 2 DrMOS and PCB’s 3D-modeling construction can be utilized to acquire parasitic inductance. Supply: Monolithic Energy Techniques
After 3D-modeling the PCB and DrMOS, the parasitic inductance will be characterised and obtained by way of ANSYS Q3D extractor. Since this text focuses on the MOSFET’s VDS spike, the primary simulation settings of curiosity are the parasitic parameters on the facility nets and driver nets.
When contemplating the parasitic element obtained from Q3D extractor, the parasitic inductance matrix—together with the self and mutual phrases of every web on the DrMOS—will be chosen below completely different frequency situations. For the reason that resonant frequency for VDS on the high-side MOSFET (HS-FET) and low-side MOSFET (LS-FET) is between 300 MHz and 500 MHz, the parasitic inductance matrix below 300 MHz situation is adopted for additional conduct mannequin simulation.
Conduct model simulation on SPICE
After the equal parasitic element mannequin is exported from Q3D, the consequences of various kinds of decoupling capacitors on the PCB are taken into consideration. Because of the capacitance decay after making use of a DC voltage on a multi-layer ceramic capacitor (MLCC), it’s vital to contemplate the equal circuit of every particular person MLCC below sure DC voltage bias situations. Every consideration ought to be based mostly on the MLCC’s working voltage. Determine 3 exhibits the circuit configuration for the conduct mannequin simulation on SPICE.
Determine 3 A circuit will be configured with a conduct mannequin simulation. Supply: Monolithic Energy Techniques
Desk 1 exhibits the simulation and measurement situations based mostly on the schematic proven in Determine 3.
Desk 1 The info exhibits the outcomes of experimental check bench. Supply: Monolithic Energy Techniques
Optimizing parasitic inductance
To suppress VDS spike with out compromising effectivity, it’s very important to optimize parasitic inductance on the PCB and package deal. With superior package deal expertise, enter capacitors will be built-in within the package deal to shorten the decoupling path (Determine 4). Paralleling the embedded capacitors within the package deal can successfully cut back the equal parasitic inductance on the DrMOS.
Determine 4 A 3D DrMOS construction with embedded capacitors optimizes the VDS spike. Supply: Monolithic Energy Techniques
Desk 2 exhibits the equal parasitic inductance and VDS spike when using completely different decoupling capacitor configurations on DrMOS.
Desk 2 Equal parasitic inductance and VDS spike are proven with completely different capacitor configurations. Supply: Monolithic Energy Techniques
Because the simulation leads to Desk 2 present, not solely is the equal parasitic inductance lowered, however the VDS spike on MOSFET can be suppressed. Furthermore, due to the MLCC’s low-ESR traits, no extra energy loss is generated on the embedded enter capacitors. Due to this fact, it’s potential so as to add completely different embedded enter capacitors to cut back parasitic inductance in DrMOS functions.
DrMOS with embedded capacitors
This text has defined the impact of parasitic inductance on the VDS switching spike, in addition to a number of strategies to stop an avalanche breakdown on the MOSFET because of the VDS switching spike. To quantify the consequences of parasitic inductance on the VDS switching spike, parasitic inductance modeling is first launched, after which conduct modeling on SPICE is proposed.
The outcomes obtained by way of SPICE carefully matched the experimental outcomes for DrMOS options such because the MP87000-L, which implies the conduct mannequin can precisely predict the danger of an avalanche breakdown on the MOSFET.
To successfully suppress the VDS spike with none tradeoffs, embedded capacitors within the package deal have been launched. The conduct mannequin simulation confirmed that these capacitors can cut back the equal parasitic inductance, and thus decrease the VDS spike with out extra loss.
Andrew Cheng is functions engineer at Monolithic Energy Techniques (MPS).
Lion Huang is senior employees functions engineer at Monolithic Energy Techniques (MPS).
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